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07/28/2023
VeriGen: A Large Language Model for Verilog Code Generation
In this study, we explore the capability of Large Language Models (LLMs)...
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06/24/2023
LLM-assisted Generation of Hardware Assertions
The security of computer systems typically relies on a hardware root of ...
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06/22/2023
FLAG: Finding Line Anomalies (in code) with Generative AI
Code contains security and functional bugs. The process of identifying a...
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06/14/2023
Qubit efficient quantum algorithms for the vehicle routing problem on quantum computers of the NISQ era
The vehicle routing problem with time windows (VRPTW) is a classic optim...
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05/22/2023
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
Logic synthesis is the first and most vital step in chip design. This st...
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03/06/2023
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Oracle-less machine learning (ML) attacks have broken various logic lock...
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02/02/2023
Fixing Hardware Security Bugs with Large Language Models
Novel AI-based code-writing Large Language Models (LLMs) such as OpenAI'...
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12/13/2022
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Automating hardware design could obviate a significant amount of human e...
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09/02/2022
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
To help prevent hardware security vulnerabilities from propagating to la...
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07/21/2022
High-Level Approaches to Hardware Security: A Tutorial
Designers use third-party intellectual property (IP) cores and outsource...
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05/26/2022
Denial-of-Service Attacks on Learned Image Compression
Deep learning techniques have shown promising results in image compressi...
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05/16/2022
ALICE: An Automatic Design Flow for eFPGA Redaction
Fabricating an integrated circuit is becoming unaffordable for many semi...
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04/05/2022
Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis
Generating sub-optimal synthesis transformation sequences ("synthesis re...
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03/10/2022
Designing ML-Resilient Locking at Register-Transfer Level
Various logic-locking schemes have been proposed to protect hardware fro...
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02/02/2022
Pop Quiz! Can a Large Language Model Help With Reverse Engineering?
Large language models (such as OpenAI's Codex) have demonstrated impress...
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12/03/2021
Can OpenAI Codex and Other Large Language Models Help Us Fix Security Bugs?
Human developers can produce code with cybersecurity weaknesses. Can eme...
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11/08/2021
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction
Semiconductor design houses rely on third-party foundries to manufacture...
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10/26/2021
Exploring eFPGA-based Redaction for IP Protection
Recently, eFPGA-based redaction has been proposed as a promising solutio...
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10/21/2021
OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis
Logic synthesis is a challenging and widely-researched combinatorial opt...
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08/20/2021
An Empirical Cybersecurity Evaluation of GitHub Copilot's Code Contributions
There is burgeoning interest in designing AI-based systems to assist hum...
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09/19/2020
Subverting Privacy-Preserving GANs: Hiding Secrets in Sanitized Images
Unprecedented data collection and sharing have exacerbated privacy conce...
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08/27/2020
DAVE: Deriving Automatically Verilog from English
While specifications for digital systems are provided in natural languag...
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06/11/2020
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking
Integrated circuits (ICs) are the foundation of all computing systems. T...
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04/26/2020
Bias Busters: Robustifying DL-based Lithographic Hotspot Detectors Against Backdooring Attacks
Deep learning (DL) offers potential improvements throughout the CAD tool...
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02/19/2020
NNoculation: Broad Spectrum and Targeted Treatment of Backdoored DNNs
This paper proposes a novel two-stage defense (NNoculation) against back...
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06/25/2019
